Dernière mise à jour : jeudi 28 mai 2015, par ,
TNT firmware mainly consist of the several bitstreams necessary to the FPGA operation.
The bitstreams can be formatted differently, depending on the way they are downloaded to the FPGA.
.bit format, to be downloaded directly to the FPGA via the JTAG port ; hence, this way of programming is volatile and the configuration is lost when the power is off
.bin format (only Virtex II), to be downloaded to a non volatile on board FLASH EPROM. From here, the bitstream can be charged to the FPGA. This opperation must be done each time the board is booted. Refer to TNT documentation for details on how this works.
.mcs format, to be stored in non volatile EEPROM’s memories via the JTAG port. At boot time, the FPGA’s recover the contents of its corresponding EEPROM’s. No special manipulation is necessary to configure.
For VHDL upgrading instructions.
The latest releases of the firmware can be downloaded here :
|When||TNT2 cards||TNT2-D cards||Notes||TUC|
Contain VHDL Spartan code V1.2(12/01/2010) and Virtex code V2.4(03/03/2010) for TNT2 cards.
Contain VHDL Spartan code V1.2(15/06/2009) and Virtex code V2.4(03/03/2010)
|Latest fixes after Jyvaskyla experiences : DDS reset fix for scanning needs, LVDS improved, E mode starting & ‘Base line averaging’ module.(see Release notes)||TUC 3.43 and later|
|14/09/2009||No yet avalaible||
Contain VHDL Spartan code V1.2(15/06/2009) and Virtex code V2.2(14/09/2009)
|New functionalities for Jyvaskyla experiences (JUROGAM-II fully equipped, 111 digital channels, 28 cards) : offset automatically adjusted by counting rates, 2 digital gain (‘old’ & ‘new’), reset amplifier and fast signal patch
(see Release notes)
|TUC 3.43 and later|
Contain Spartan VHDL code (10/11/2004) and Virtex VHDL code (05/07/2007)
Contain Spartan VHDL code (03/05/2007) and Virtex VHDL code (05/07/2007)
|New mix mode and lot of stuff (see Release notes)||TUC 3.2 and later|
Contain Spartan VHDL code (10/11/2004) and Virtex VHDL code (15/02/2007)
Contain Spartan VHDL code (28/06/2006) and Virtex VHDL code (15/02/2007)
|Energy : digital gain is improved, trapezoid rise time k has max value increased to 20470 ns and ability to mark & readout events when ADC is out of range (or reject)||TUC 2.3.3|
Contain Spartan VHDL code (10/11/2004) and Virtex VHDL code (06/10/2006)
Contain Spartan VHDL code (28/06/2006) and Virtex VHDL code (06/10/2006)
|See Release notes||TUC 2.3.2x|
Some firmware is also stored in the FX2 USB chip which has in charge all the low level USB communication and act as some gateway to both FPGA. This firmware (which contain the card number) is stored in some IIC EEPROM.